In deep sub-micro designs, more functions are integrated into one chip, and datapath has become a critical part of the design. A typical datapath comprises an array of bit slices. However, existing design methodologies may generate inferior datapath designs because the datapath regularity cannot be well understood by traditional design tools. For example, several techniques are proposed to preserve/re-identify datapath structures. However, such techniques either restrict the datapath optimization or have little tolerance on bit slice difference.